The present invention relates to semiconductor wafers, a method for processing the same and a method for manufacturing semiconductor devices. The present invention particularly relates to semiconductor wafers having element isolation regions, a method for processing the same and a method for manufacturing semiconductor devices.
With the miniaturization of semiconductor devices (for example, MOS transistors) promoted in recent years, a further miniaturization of element isolation regions in semiconductor devices is required. In order to achieve a further miniaturization of element isolation regions in semiconductor devices, a trench isolation technique has been introduced. In the trench isolation technique, trenches are provided between semiconductor elements on a semiconductor substrate, and a dielectric material is filled in the trenches to isolate the semiconductor elements from one another. One example of the element isolation technique will be described below.
FIGS. 11 through 13 schematically show steps of forming element isolation regions using a conventional trench isolation technique. FIG. 11 is a plan view of a semiconductor wafer over which a pad layer, a polishing stopper layer and a resist layer are successively deposited, and also shows, for description purposes, a range of exposure of the resist layer formed over the semiconductor wafer. FIGS. 12 and 13 schematically show cross-sectional views taken along a line Bxe2x80x94B of FIG. 11 in different steps.
First, a pad layer 112, a polishing stopper layer 114 and a resist layer R2 are successively deposited over a semiconductor wafer 110. Then, as shown in FIG. 11, the resist layer R2 only in a chip region 120 is exposed.
Next, as shown in FIG. 12(a), the resist layer R2 is developed to form the resist layer R2 into a specified pattern. Then, the polishing stopper layer 114 and the pad layer 112 are removed using the resist layer R2 as a mask.
Then, as shown in FIG. 12(b), the resist layer R2 is removed and trenches 132 are formed in the semiconductor wafer 110 using the polysilicon layer 114 as a mask.
As shown in FIG. 13(a), a dielectric layer 152 is formed over the semiconductor wafer 110 in a manner to fill the trenches 132 with the dielectric layer 152.
Next, as shown in FIG. 13(b), the dielectric layer 152 is polished by a chemical-mechanical polishing method (hereafter referred to as a xe2x80x9cCMP methodxe2x80x9d). Through the steps described above, the dielectric layer 152 is embedded in the trenches 132, and thereby trench isolation regions are formed.
In order to prevent the throughput of the exposure step from lowering, the resist layer R2 in the non-chip region 122 is not generally exposed, as shown in FIG. 11. As a result, as shown in FIG. 12(b), after the trenches 132 are formed in the semiconductor wafer 110, a relatively wide convex region 160 is formed in the non-chip region 122 adjacent to the chip region 120. The relatively wide convex region 160 formed in the non-chip region 122 adjacent to the chip region 120 causes the following problems.
As shown in FIG. 13(a), when the dielectric layer 152 is formed over the semiconductor wafer 110, the dielectric layer 152 is thickly deposited over the wide convex region 160. If the dielectric layer 152 is polished while the dielectric layer 152 is thickly deposited in the wide convex region 160, the dielectric layer 152 deposited in the wide convex region 160 remains more than the dielectric layer 152 deposited over the chip region 120. Also, due to the presence of the thick dielectric layer 152 formed in the wide convex region 160, the dielectric layer 152 remains in an area over a convex section 162 adjacent to the wide convex region 160. In other word, the dielectric layer 152 in the chip region 120 remains in an area over the convex section 162 adjacent to the non-chip region 122. When the dielectric layer 152 in the chip region 120 remains in an area over the convex section 162 adjacent to the non-chip region 122, the polishing stopper layer 114 cannot be removed, and a semiconductor element cannot be formed over the convex section 162.
Furthermore, if the dielectric layer 152 is polished while the dielectric layer 152 is thickly deposited in the wide convex region 160, the thinning and dishing phenomenon occur. These phenomenon cause variations in the thickness of the dielectric layer 152.
Because of the reasons described above, when the relatively wide convex region 160 is formed in the non-chip region 122 adjacent to the chip region 120, chips that are formed in outermost areas (areas indicated by crosses (x) in FIG. 11) of the chip region 120 may become bad chips. In other words, the yield of chips formed in the chip region other than the outermost areas is lowered.
(1) In accordance with a first embodiment of the present invention, a method is provided for processing a semiconductor wafer having a chip region and a non-chip region. In accordance with the method, a dummy trench isolation region is formed in at least a part of the non-chip region of the semiconductor wafer.
The xe2x80x9cchip regionxe2x80x9d used here refers to a region in a semiconductor wafer where chips can be formed according to a specified pattern, and the xe2x80x9cnon-chip regionxe2x80x9d used here refers to a region in the semiconductor wafer where chips cannot be formed according to the specified pattern.
In the method for processing a semiconductor wafer in accordance with the first embodiment, a dummy trench isolation region is formed in at least a part of the non-chip region of the semiconductor wafer. In other words, when trenches are formed in the semiconductor wafer to form trench isolation regions in the semiconductor wafer, dummy trenches are formed in the non-chip region. As a result, when a dielectric layer is filled in the trenches, the dielectric layer is prevented from being thickly deposited in a convex region in the non-chip region. Therefore, when the dielectric layer is polished, the dielectric layer is prevented from remaining in convex sections in the chip region adjacent to the non-chip region by the influence of the dielectric layer deposited over the non-chip region.
(2) In accordance with a second embodiment of the present invention, a semiconductor wafer having a chip region and a non-chip region is processed by a method including the step of forming trench isolation regions in the semiconductor wafer. In one aspect of the second embodiment of the present invention, the trench isolation regions may be formed by a method including at least the following steps. (a) A polishing stopper layer having a specified pattern is formed over the semiconductor wafer. (b) Trenches in the chip region and dummy trenches in at least a portion of the non-chip region in the semiconductor wafer are formed using at least the polishing stopper layer as a mask. (c) A dielectric layer is formed over the semiconductor wafer in a manner to fill the trenches and the dummy trenches with the dielectric layer. (d) The insulation layer is polished using the polishing stopper layer as a stopper.
The method for processing a semiconductor wafer in accordance with the second embodiment of the present invention provides the same effects as those provided by the first embodiment of the present invention.
(3) In accordance with a third embodiment of the present invention, a semiconductor wafer having a chip region and a non-chip region is processed by a method including the step of forming trench isolation regions in the semiconductor wafer. In one aspect of the third embodiment of the present invention, the trench isolation regions may be formed by a method including at least the following steps. (h) A polishing stopper layer is formed over the semiconductor wafer. (i) A resist layer is formed over the polishing stopper layer. (j) The resist layer in the chip region and at least one specified portion of the non-chip region are exposed. (k) The resist layer is developed. (l) The polishing stopper layer is removed in a specified pattern using the resist layer as a mask. (m) The semiconductor wafer is etched using at least the polishing stopper layer to form trenches in the chip region and dummy trenches in the non-chip region. (n) A dielectric layer is formed over the semiconductor wafer in a manner to fill the trenches and the dummy trenches with the dielectric layer. (o) The insulation layer is polished using the polishing stopper layer as a stopper.
The method for processing a semiconductor wafer in accordance with the third embodiment of the present invention provides the same effects as those provided by the first embodiment of the present invention.
In the method for processing a semiconductor wafer in accordance with the third embodiment of the present invention, a photomask may preferably be used in the step (j) to simultaneously expose the resist layer in the chip region and the at least one specified portion of the non-chip region.
As a result, the throughput in the exposure step is improved compared to the case in which different photomasks are used to expose the resist layer in the chip region and the at least one specified portion of the non-chip region, respectively.
In accordance with an embodiment of the present invention, a semiconductor wafer comprises a chip region and a non-chip region, wherein at least one portion of the non-chip region includes at least one dummy trench isolation region.
When semiconductor devices are manufactured using a semiconductor wafer that is processed in accordance with the embodiment of the present invention, the yield of chips in a chip region adjacent to a non-chip region of the semiconductor wafer is increased for the reasons described above in conjunction with the description of the method for processing semiconductor wafers.
In accordance with an embodiment of the present invention, a method for manufacturing a semiconductor device includes any one of the semiconductor wafer processing methods described above.
By the method for manufacturing a semiconductor device in accordance with the present embodiment of the present invention, the yield of chips in a chip region adjacent to a non-chip region of the semiconductor wafer is increased for the reasons described above in conjunction with the description of the method for processing semiconductor wafers.